With advancements in electronics technology, the need for faster processing and data storage has increased. As the scaling of metal-oxide-semiconductor field-effect transistor (MOSFET) technology has progressed, the industry has faced various challenges, including increased short-circuit effects, reduced gate control, exponential leakage current, and power dissipation. Field-effect transistors made from Carbon nanotubes are a suitable replacement for MOSFETs. 4-to-2 compressors are among the most popular bit compression cells that are widely used in multiplication or multi-operand addition. Their most important function is to increase the performance and efficiency of multiplication compression calculations. After examining twelve different 4-to-2 compressor designs from various research papers, this article presents a novel 4-to-2 compressor architecture utilizing modified logical relationships and Carbon nanotube technology. The proposed 4-to-2 compressor and other designs from the literature have been implemented using the HSPICE simulation software. The proposed design and the previous compressors have been compared in terms of power consumption, delay, transistor count, and accuracy. Simulation results demonstrate that the new compressor architecture achieves a 25% reduction in power consumption, an 18% decrease in delay, and a 12% reduction in transistor count compared to the best previous compressor.

We present the design and simulation of a single-walled Carbon nanotube (SWCNT)-based field-effect transistor (FET) using Silvaco TCAD. In this paper, the self-heating effect modeling of the CNT MOSFET structure is performed and compared with conventional MOSFET structure having same channel length. The numerical results are presented to show the self-heating effect on the I– V characteristics of the CNT MOSFET and conventional MOSFET structures. Results from numerical simulation show that the maximum temperature rise and the performance degradation of the CNT MOSFET are quite lower than that of the conventional MOSFET counterpart. These advantages are contributed by the good electrical and thermal properties of the SWCNTs. Therefore, SWCNT materials have a high capability for the development of active devices with low power dissipation and good reliability at high operating temperature.

The multiplier is the basic computational operation in ALUs and impacts on their performance and chip size. Carbon nanotube field effect transistors (CNFETs) are used in many designs to enhance their performance, area, and power dissipation. Moreover, using CNFET results multi-value logic (MVL) -i.e., ternary logic. Using ternary logic in circuits results in chip size reduction due to its less connection than binary logic. In this paper, two novel ternary multipliers based on CNFET are proposed. The number of transistors is reduced about 15% in the first proposed design compared with the best-reported result. The PDP of the second proposed circuit is reduced about 57% in comparison with the best design. Stanford's 32-nanometer model, the HSPICE software, and same input signals are used to investigate the criteria of simulation of multiplier circuits.

Since 1993, Devices based on CNTs have applicationsranging from nanoelectronics to optoelectronics. Thechallenging issue in designing these devices is that thenonequilibrium Green's function (NEGF) method has tobe employed to solve the Schrödinger and Poissonequations, which is complex and time consuming. In thepresent study, a novel smart and optimal algorithm ispresented for fast and accurate modeling of CNT fieldeffecttransistors (CNTFETs) based on an artificial neuralnetwork. A new and efficient way is presented forincrementally constructing radial basis function (RBF)networks with optimized neuron radii to obtain theestimator network. An incremental extreme learningmachine (I-ELM) algorithm is used to train the RBFnetwork. To ensure the optimal radii for incrementalneurons, this algorithm utilizes a modified version of anoptimization algorithm known as the Nelder-Meadsimplex algorithm. Results confirm that the proposedapproach reduces the network size for faster errorconvergence while preserving the estimation accuracy.

Underlap between gate and drain/source area is one of the important items non-ideal effects in the device manufacturing process in the nanometer scale. In this paper, for the first time, the effect of underlap between the gate and drain/source area for tunneling Carbon nanotube field effects transistor is investigated. To simulate the device, self-consistent solution of Schrodinger and Poisson equations and Non-equilibrium Green’ s Function method have been employed. The function of the device is evaluated in terms of the on-state current, off-state current, current ratio, sub-threshold swing, delay time, and the power delay product. The simulation results show that the underlap effect improves some of the device characteristics and has some adverse effects on other characteristics. In the case where the length of underlap area is optimally chosen, the device performance will be improved considerably. Simulation results indicate that underlap significantly reduces the off-state current and thus reduces band-to-band tunneling and ambipolar behavior of the device. Also, the underlap effect by improving the power delay product parameter is a suitable option for low power applications compared with the conventional structure.

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless Carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different workfunctions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less than the work-function of the intrinsic Carbon nanotube. The simulation is carried out in the ballistic regime using the non-equilibrium Green’s function (NEGF) in the mode space approach. The simulation results show that the proposed structure has a better am-bipolar behavior and less OFF current compared to a conventional junctionless structure with the same dimensions. In the new structure, the hot carrier effect is also reduced due to the reduced electric field near the drain, and with regard to a peak in the electric field curve at the junction of two gates, the gate control on the channel will be increased.